1. Field of the Invention
The present invention concerns a method of manufacturing a semiconductor substrate and, more particularly, it relates to a method of manufacturing a multi-layered semiconductor substrate for forming circuit elements such as transistors on a single crystal semiconductor substrate formed on an insulation material.
2. Description of the Prior Art
There has been made an attempt of manufacturing semiconductor integrated circuits with less stray capacity by isolating circuit elements with dielectric material for improving the performance of semiconductor devices and an attempt of manufacturing so-called three dimensional circuit devices in which circuit elements are laminated in a three dimensional manner. As one of such methods, there has been known a method of forming a non-single crystal semiconductor layer on an insulation layer, and heating only the surface layer thereof by the irradiation of energy rays such as laser beams, thereby forming a single crystal semiconductor layer. In this case, there has been attempted to partially dispose an opening, that reaches a semiconductor single crystal substrate, to the insulation material and to prevail the melting at the non-single crystal semi-conductor layer to the surface of the single crystal semiconductor substrate at the opening, thereby making the non-single crystal semiconductor layer into single crystals having the identical axis of crystallization with that of the single crystals in the substrate.
FIG. 1 is a plan view for the conventional semiconductor substrate just before the irradiation of energy-rays and FIG. 2 is a cross sectional view taken along line II--II in FIG. 1.
Explanation is to be made for the constitution while referring to both of the figures. At first, an oxide film 2 as a first insulation film comprising silicon dioxide is formed to a thickness of 1 .mu.m on a silicon substrate 1, which is a semiconductor substrate comprising single crystals and having a main surface, and openings 3 reaching the silicon substrate 1 are disposed at predetermined positions. Then, polycrystalline silicon 5 is deposited to a thickness of 0.5 .mu.m on the oxide film 2 also including the inside of the openings 3 by way of a chemical gas phase growing method (CVD method) and, an oxide film 6 as a second insulation film is deposited further thereover to a thickness of 100 .ANG. also by way of the CVD method. Further, a nitride film 7 is deposited in a stripe-like manner to a thickness of 500 .ANG. over the oxide film 6 at the positions above the openings 3 by means of the CVD method. Furthermore, a nitride film 12 each of 5 .mu.m width is formed at 10 .mu.m distance to a thickness of 500 .ANG. on the oxide film 6 put between the nitride films 7 also by means of the CVD method. The opening 3 is usually referred to as a scribe line having 100-200 .mu.m width and 10-20 mm length, which is disposed as a region for isolating the chips of a semiconductor integrated circuit.
FIG. 3 is a cross sectional view of a semiconductor substrate during irradiation of the energy-rays.
The irradiation state is to be explained referring to the drawing. Continuously oscillating argon laser beams 9 restricted to 100 .mu.m diameter are irradiated to the semiconductor substrate of the structure as shown in FIG. 3 under scanning at a scanning rate of 25 cm/s to melt the polycrystalline silicon 5. Solidification and recrystallization of the melted molten silicon 10 occurs from the single crystal silicon substrate 1 at the opening 3 toward the polycrystalline silicon 5 on the oxide film 2, and the polycrystalline silicon 5 on the oxide film 2 is formed into a single crystalline silicon 11 having the same axis of crystallization with that of the single crystal silicon of the substrate 1 after ending the laser beam irradiation. In this case, the nitride film 7 over the opening 3 functions as the reflection preventive film for the laser beams upon irradiation thereof and it is disposed for preventing the lowering of the polycrystalline silicon temperature in the opening 3 showing greater heat diffusion than the oxide film 2. Further, the nitride film 12 disposed in the stripe-like manner on the polycrystalline silicon 5 on the oxide film 2 is disposed for controlling the lateral temperature distribution in the polycrystalline silicon 5 upon laser beam irradiation, so that the growth of the single crystals occurs continuously over the entire chip. The mechanism for the recrystallization is specifically described in Japanese Patent Application No. Sho 61-48468. Further, the oxide film 6 is disposed so that nitrogen in the nitride films 7 and 12 may not intrude into the molten silicon 10 melted upon laser beam irradiation. After the laser beam irradiation is completed and the polycrystalline silicon 5 in the chip is formed into single crystals, the nitride films 7, 12 and the oxide film 6 are removed and, subsequently, circuit elements are formed on the single-crystallized silicon 11 on the oxide film 2 by the usual production process for the integrated circuit. After all of the processes as described above have been completed, the semiconductor substrate is scribed along the openings 3 to complete individual semiconductor integrated circuit chips each of 10-20 mm square. Accordingly, the opening 3 has a function of producing a single-crystallized silicon film 11 having the same axis of crystallization as that of the single crystal silicon substrate 11 on the oxide film 2 and a function of the scribe line for scribing the semiconductor circuit chips after the completion of all of the processes.
In the conventional production process as described above, the opening 3 is formed linearly over a large region. Accordingly, since the temperature distribution upon melting of the polycrystalline silicon 5 in the opening 3 and the polycrystalline silicon 5 on the oxide film 2 are different (the temperature of polycrystalline silicon 5 on the oxide film 2 is higher), the viscosity of the molten silicon 10 situated on the oxide film 2 is lower. Therefore, the film thickness of the polycrystalline silicon 5 on the oxide film 2 adjacent with the end of the opening 3 is decreased upon recrystallization (single crystallization) by the surface tension exerted to the boundary between the oxide films 2 and 6.
FIG. 4 is a cross sectional view for the semiconductor substrate illustrating such a state.
As shown in the drawing, the polycrystalline silicon 5 on the oxide film 2 at the end of the opening 3 is recessed as a pit portion 15 and the polycrystalline silicon 5 on the oxide film 2 at the end of the opening 3 in the downward side of the scanning is bulged by so much as the recess to form a protrusion 16. The recess may sometimes increase further and the single-crystallized silicon 11 at the end of the opening 3 is eliminated by the movement of the molten silicon 10 upon melting (the film thickness is reduced to 0). It is apparent that this problem can be overcome if the temperature of the polycrystalline silicon 5 upon melting could be made uniform at the opening 3 and on the oxide film 2. However, it has been actually difficult, in view of the cost, to make the temperature uniform in various structures. It has been further attempted to make the temperature uniform by reducing the size of the opening 3 for overcoming the problem.
FIG. 5 is a plan view illustrating this embodiment and FIG. 6 is a cross sectional view taken along line VI--VI in FIG. 5.
Referring to both of the drawings, the opening is not formed in the region of the scribe line 17 but square form openings 18 each of 5 .mu.m on a side are disposed at 15 .mu.m intervals near the scribe line 17. By reducing the size of the openings and disposing them in a scattered manner, since the non-uniformity of the temperature upon melting the polycrystalline silicon 5 is limited to the size-reduced openings 18, the non-uniformity for the film thickness of the polycrystalline silicon 5 after recrystallization is reduced and the problem in the production of the circuit elements can be avoided. However, since it is actually necessary to dispose linear openings such as alignment marks for the mask alignment in the subsequent step, it brings about various practical problems in reducing the size for all of the openings and disposing them in a scattered manner.